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FSB50450S Smart Power Module (SPM)
September 2006
FSB50450S
Smart Power Module (SPM) Features
* 500V 3.0A 3-phase FRFET inverter including high voltage integrated circuit (HVIC) * 3 divided negative dc-link terminals for inverter current sensing applications * HVIC for gate driving and undervoltage protection * 3/5V CMOS/TTL compatible, active-high interface * Optimized for low electromagnetic interference * Isolation voltage rating of 1500Vrms for 1min. * Surface mounted device package * Moisture Sensitive Level 3
General Description
FSB50450S is a tiny smart power module (SPM) based on FRFET technology as a compact inverter solution for small power motor drive applications such as fan motors and water suppliers. It is composed of 6 fast-recovery MOSFET (FRFET), and 3 half-bridge HVICs for FRFET gate driving. FSB50450S provides low electromagnetic interference (EMI) characteristics with optimized switching speed. Moreover, since it employs FRFET as a power switch, it has much better ruggedness and larger safe operation area (SOA) than that of an IGBT-based power module or one-chip solution. The package is optimized for the thermal performance and compactness for the use in the built-in motor application and any other application where the assembly space is concerned. FSB50450S is the most solution for the compact inverter providing the energy efficiency, compactness, and low electromagnetic interference.
Absolute Maximum Ratings
Symbol
VPN1 VPN2 ID25 ID80 IDP PD VCC VBS VIN TJ TSTG RJC VISO
Parameter
DC Link Input Voltage, Drain-source Voltage of each FRFET Each FRFET Drain Current, Continuous Each FRFET Drain Current, Continuous Each FRFET Drain Current, Peak Maximum Power Dissipation Control Supply Voltage High-side Bias Voltage Input Signal Voltage Operating Junction Temperature Storage Temperature Junction to Case Thermal Resistance Isolation Voltage TJ = 25C TJ = 150C TC = 25C TC = 100C
Conditions
Rating
500 500 1.5 1.0 3.0 14 20 20 -0.3 ~ VCC+0.3 -20 ~ 150 -50 ~ 150
Units
V V A A A W V V V C C C/W Vrms
TC = 25C, PW < 100s TC = 25C, Each FRFET Applied between VCC and COM Applied between VB(U)-VS(U), VB(V)-VS(V), VB(W)-VS(W) Applied between IN and COM
Each FRFET under inverter operating condition (Note 1) 60Hz, Sinusoidal, 1 minute, Connection pins to heatsink
8.9 1500
(c)2006 Fairchild Semiconductor Corporation
1
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FSB50450S Rev. A
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FSB50450S Smart Power Module (SPM)
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Pin Name
COM VB(U) VCC(U) IN(UH) IN(UL) VS(U) VB(V) VCC(V) IN(VH) IN(VL) VS(V) VB(W) VCC(W) IN(WH) IN(WL) VS(W) P U, VS(U) NU NV V, VS(V) NW W, VS(W) IC Common Supply Ground
Pin Description
Bias Voltage for U Phase High Side FRFET Driving Bias Voltage for U Phase IC and Low Side FRFET Driving Signal Input for U Phase High-side Signal Input for U Phase Low-side Bias Voltage Ground for U Phase High Side FRFET Driving Bias Voltage for V Phase High Side FRFET Driving Bias Voltage for V Phase IC and Low Side FRFET Driving Signal Input for V Phase High-side Signal Input for V Phase Low-side Bias Voltage Ground for V Phase High Side FRFET Driving Bias Voltage for W Phase High Side FRFET Driving Bias Voltage for W Phase IC and Low Side FRFET Driving Signal Input for W Phase High-side Signal Input for W Phase Low-side Bias Voltage Ground for W Phase High Side FRFET Driving Positive DC-Link Input Output for U Phase & Bias Voltage Ground for High Side FRFET Driving Negative DC-Link Input for U Phase Negative DC-Link Input for V Phase Output for V Phase & Bias Voltage Ground for High Side FRFET Driving Negative DC-Link Input for W Phase Output for W Phase & Bias Voltage Ground for High Side FRFET Driving
(1) COM (2) VB(U) (3) VCC(U) (4) IN(UH) (5) IN(UL) (6) VS(U) (7) VB(V) (8) VCC(V) (9) IN(VH) (10) IN(VL) (11) VS(V) (12) VB(W) (13) VCC(W) (14) IN(WH) (15) IN(WL) (16) VS(W)
Note: Source terminal of each MOSFET is not connected to supply ground or bias voltage ground inside SPM. External connections should be made as indicated in Figure 2 and 5.
(17) P VCC HIN LIN COM VB HO VS LO (19) NU VCC HIN LIN COM VB HO VS LO (21) V (20) NV (18) U
VCC HIN LIN COM
VB HO VS LO
(22) NW (23) W
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
2 FSB50450S Rev. A
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FSB50450S Smart Power Module (SPM)
Electrical Characteristics (TJ = 25C, VCC=VBS=15V Unless Otherwise Specified)
Inverter Part (Each FRFET Unless Otherwise Specified) Symbol
BVDSS1 BVDSS2 BVDSS/ TJ IDSS RDS(on) VSD tON tOFF trr EON EOFF RBSOA (Note 3) V = 400V, VCC = VBS = 15V, ID = IDP, VDS=BVDSS, Reverse-bias Safe Oper- PN TJ = 150C ating Area High- and low-side FRFET switching (Note 4) Switching Times
Parameter
Conditions
Min Typ Max Units
500 500 0.53 1.9 1152 600 185 85 11 250 2.4 1.2 V V V A V ns ns ns J J
Drain-Source Breakdown VIN= 0V, ID = 250A (Note 2) Voltage VIN= 0V, ID = 250A, TJ = 150C Breakdown Voltage TemID = 250A, Referenced to 25C perature Coefficient Zero Gate Voltage Drain Current Static Drain-Source On-Resistance Drain-Source Diode Forward Voltage VIN= 0V, VDS = 500V VCC = VBS = 15V, VIN = 5V, ID = 1.0A VCC = VBS = 15V, VIN = 0V, ID = -1.0A VPN = 300V, VCC = VBS = 15V, ID = 1.0A VIN = 0V 5V Inductive load L=3mH High- and low-side FRFET switching
Full Square
Control Part (Each HVIC Unless Otherwise Specified) Symbol
IQCC IQBS UVCCD UVCCR UVBSD UVBSR VIH VIL IIH IIL
Note: 1. For the measurement point of case temperature TC, please refer to Figure 3 in page 4. 2. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM. VPN should be sufficiently less than this value considering the effect of the stray inductance so that VDS should not exceed BVDSS in any case. 3. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 4 for the switching time definition with the switching test circuit of Figure 5. 4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 5 for the RBSOA test circuit that is same as the switching test circuit.
Parameter
Quiescent VCC Current Quiescent VBS Current Low-side Undervoltage Protection (Figure 6) High-side Undervoltage Protection (Figure 7) ON Threshold Voltage OFF Threshold Voltage Input Bias Current VCC=15V, VIN=0V VBS=15V, VIN=0V
Conditions
Applied between VCC and COM Applied between VB(U)-VS(U), VB(V)-VS(V), VB(W)-VS(W)
Min Typ Max Units
7.4 8.0 7.4 8.0 3.0 8.0 8.9 8.0 8.9 10 160 100 9.4 9.8 9.4 9.8 0.8 20 2 A A V V V V V V A A
VCC Undervoltage Protection Detection Level VCC Undervoltage Protection Reset Level VBS Undervoltage Protection Detection Level VBS Undervoltage Protection Reset Level Logic High Level Logic Low Level VIN = 5V VIN = 0V Applied between IN and COM
Applied between IN and COM
3 FSB50450S Rev. A
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FSB50450S Smart Power Module (SPM)
Recommended Operating Conditions
Symbol
VPN VCC VBS VIN(ON) VIN(OFF) tdead fPWM
Parameter
Supply Voltage Control Supply Voltage High-side Bias Voltage Input ON Threshold Voltage Input OFF Threshold Voltage
Conditions
Applied between P and N Applied between VCC and COM Applied between VB and VS Applied between IN and COM
Value Min.
13.5 13.5 3.0 0 1.0 -
Typ.
300 15 15 15
Max.
400 16.5 16.5 VCC 0.6 -
Units
V V V V V s kHz
Blanking Time for Preventing VCC=VBS=13.5 ~ 16.5V, TJ 150C Arm-short PWM Switching Frequency TJ 150C
These values depend on PWM control algorithm
15-V Line R1 D1 VCC HIN LIN C5 COM VB HO VS LO N C2 C1 One-Leg Diagram of SPM * Example of bootstrap paramters: C1 = C2 = 1F ceramic capacitor, R1 = 56, R2 = 20 R3 R2 P VDC
HIN 0
LIN 0 1 0 1 Open
Output Z 0 VDC Forbidden Z
Note Both FRFET Off Low-side FRFET On High-side FRFET On Shoot-through Same as (0, 0)
R5
Inverter Output C3
0 1 1 Open
Micom
10F
Note: (1) It is recommended the bootstrap diode D1 to have soft and fast recovery characteristics with 600-V rating (2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above. (3) RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM is compatible with standard CMOS or LSTTL outptus. (4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2 and C3 should have good high-frequency characteristics to absorb high-frequency ripple current.
Figure 2. Recommended CPU Interface and Bootstrap Circuit with Parameters
14.50mm
3.80mm
MOSFET
Note:
Case Temperature(Tc) Detecting Point
Attach the thermocouple on top of the heatsink-side of SPM (between SPM and heatsink if applied) to get the correct temperature measurement.
Figure 3. Case Temperature Measurement
4 FSB50450S Rev. A
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FSB50450S Smart Power Module (SPM)
VIN Irr VDS 100% of ID 120% of ID
VIN
ID
10% of ID ID VDS
tON
trr
tOFF
(a) Turn-on
(b) Turn-off
Figure 4. Switching Time Definition
REH VCC RBS VCC HIN LIN COM VB HO VS LO + VDS L VDC ID
CBS
One-leg Diagram of SPM
Figure 5. Switching and RBSOA(Single-pulse) Test Circuit (Low-side)
Input Signal UV Protection Status
RESET
DETECTION
RESET
Low-side Supply, VCC
UVCCR UVCCD
MOSFET Current
Figure 6. Undervoltage Protection (Low-side)
Input Signal UV Protection Status
RESET
DETECTION
RESET
High-side Supply, VBS
UVBSR UVBSD
MOSFET Current
Figure 7. Undervoltage Protection (High-side)
5 FSB50450S Rev. A
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FSB50450S Smart Power Module (SPM)
R2
(1) COM R1 R5 (2) VB(U) (3) VCC(U) (4) IN(UH) (5) IN(UL) C5 R1 C2 C1 (6) VS(U) (7) VB(V) (8) VCC(V) (9) IN(VH) VCC HIN LIN COM VB HO VS LO VCC HIN LIN COM VB HO VS LO (19) NU (20) NV (21) V (18) U C3 VDC (17) P
Micom
(10) IN(VL) C2 R1 C1 (11) VS(V) (12) VB(W) (13) VCC(W ) (14) IN(WH) (15) IN(WL) C2 C1 (16) VS(W)
M
VCC HIN LIN COM
VB HO VS LO
(22) NW (23) W
For 3-phase current sensing and protection 15-V Supply
R4
C4
R3
Figure 8. Example of Application Circuit
6 FSB50450S Rev. A
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FSB50450S Smart Power Module (SPM)
Detailed Package Outline Drawings
Max 1.00 0.600.10
(1.165)
15*1.778=26.670.30
15*1.778=26.67 13.340.30 #1 13.340.30 #16 #1 #16
1.30 12.000.20 12.30 2.48 15.60 (1.00) (1.80) 17.000.20 17.90
4.43
#17 12.230.30 29.000.20 13.130.30
#23
2.80
7.80
LAND PATTERN RECOMMENDATIONS
2x3.90=7.800.30 (2.275) 4x3.90=15.600.30 1.95 (1.80) 3.100.20 (1.30)
0.600.10 Max 1.00
0 0.50+0.15 -0.0
Max 3.50
0.508
GAGE PLANE
(2.50)
5 3
(1.30)
0.150.05
SEATING PLANE
1.500.20
7 FSB50450S Rev. A
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FSB50450S Smart Power Module (SPM)
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM
ActiveArrayTM BottomlessTM CoolFETTM CROSSVOLTTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
FAST(R) FASTrTM FPSTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM I2CTM i-LoTM ImpliedDisconnectTM
Across the board. Around the world.TM The Power Franchise(R) Programmable Active DroopTM
IntelliMAXTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM
POPTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER(R) SMART STARTTM
SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET(R) UniFETTM VCXTM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I15
8 FSB50450S Rev. A
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